I am designing an RP2350 based dev board where, because the RP2350 will interface with FPGA IO banks that are 1.8V max, RP2350 IOVDD will be 1.8V. I have a couple of choices for ADC_AVDD: 1.8V or 3.3V.One way to read the note above is that, in the scenario described, which is the same as mine, it is better for ADC_AVDD to be 3.3V (so long as the voltage on the IO does not exceed 1.8V). However, that will throw away almost one bit of precision (3.3/1.8 = 1.83). Can anyone confirm that 3.3V is actually the better of the two options in this case?
Statistics: Posted by alastairpatrick — Wed Feb 05, 2025 12:24 am — Replies 0 — Views 11