Hello, I'm evaluating the CM5 to create a ZFS based NAS, were ECC memory is very important, but cannot find detalis about the claimed ECC memory protection support on the CM5. From my understanding these are the possible ECC kinds:
Traditional ECC: Uses special RAM chips, recoverable parity errors are fixed on the fly by the chips and reported to the OS kernel so you can be alerted about a faulty RAM (thru EDAC on Linux), and non-recoverable parity errors are reported by the chips to the OS kernel so the OS can kill the process that is using the faulty memory region and blacklist it to mitigate error propagation.
On-Die ECC / ODECC / on-chip ECC: usually the default for DDR5 modules, recoverable parity errors are silently fixed by the chips and never reported to the OS, and non-recoverable parity errors aren't reported neither. Less safety than Traditional ECC.
In-Band ECC / IBECC: Normal memory modules are used, but the CPU/Memory Controller has an special circuitry so 1/32 of the available RAM is reserved for parity bits, and every write/read also writes/checks parity bits. CPU's like the Intel N97 / N100 have support for it (the BIOS must provide the option, like in the Odroid-H4+). Recoverable parity errors are fixed by the CPU and reported to the OS and non-recoverable are reported by the CPU to the OS. To my knowledge, provides the same safety level as Traditional ECC without requiring special RAM chip.
My questions are:
- What kind of ECC the Raspberry CM5 has?
- Did the Linux kernel receive reports?
- There is a way to test it (e.g. IBECC CPUs provide instructions to inject an artificial ECC error).
Traditional ECC: Uses special RAM chips, recoverable parity errors are fixed on the fly by the chips and reported to the OS kernel so you can be alerted about a faulty RAM (thru EDAC on Linux), and non-recoverable parity errors are reported by the chips to the OS kernel so the OS can kill the process that is using the faulty memory region and blacklist it to mitigate error propagation.
On-Die ECC / ODECC / on-chip ECC: usually the default for DDR5 modules, recoverable parity errors are silently fixed by the chips and never reported to the OS, and non-recoverable parity errors aren't reported neither. Less safety than Traditional ECC.
In-Band ECC / IBECC: Normal memory modules are used, but the CPU/Memory Controller has an special circuitry so 1/32 of the available RAM is reserved for parity bits, and every write/read also writes/checks parity bits. CPU's like the Intel N97 / N100 have support for it (the BIOS must provide the option, like in the Odroid-H4+). Recoverable parity errors are fixed by the CPU and reported to the OS and non-recoverable are reported by the CPU to the OS. To my knowledge, provides the same safety level as Traditional ECC without requiring special RAM chip.
My questions are:
- What kind of ECC the Raspberry CM5 has?
- Did the Linux kernel receive reports?
- There is a way to test it (e.g. IBECC CPUs provide instructions to inject an artificial ECC error).
Statistics: Posted by nahuel0x — Tue Feb 18, 2025 11:05 pm — Replies 1 — Views 37