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General • PIO PWM 0 Duty != 0

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I'm having a problem with PWM implemented in the PIO whereby when I set the Duty to 0 there is still a very brief pulse (of a few nS / 1 clk cycle).

I cant see how this happens but commenting out the `set pins` lines does stop it happening so it would seem I am missing something to do with how this code is working:

Code:

.program pwm    set pins, 0b00    pull noblock           ; Pull from FIFO to OSR if available, else copy X to OSR.    mov x, osr             ; Copy most-recently-pulled value back to scratch X. This is the PWM Duty.    mov y, isr             ; ISR contains PWM period. Y used as counter.countloop1:    jmp x!=y noset1         ; Set pin high if X == Y, keep the two paths length matched    set pins, 0b10    jmp skip1noset1:    nop                    ; Single dummy cycle to keep the two paths the same lengthskip1:    jmp y-- countloop1      ; Loop until Y hits 0, then repeat for the second output        set pins, 0b00    mov y, isr             ; ISR contains PWM period. Y used as counter.countloop2:    jmp x!=y noset2         ; Set pin high if X == Y, keep the two paths length matched    set pins, 0b01    jmp skip2noset2:    nop                    ; Single dummy cycle to keep the two paths the same lengthskip2:    jmp y-- countloop2      ; Loop until Y hits 0
There out 2 outputs which are each driven alternately for the desired duty/period.
Both outputs are set off.
x is loaded with the duty, y with the period.
y is decremented and at some point becomes equal to x, the duty, at which point an output is switched on.
when y reaches 0 the output is switched back off and the process repeats for the other output.

Now when 0 is loaded into x (e.g.: pio_sm_put_blocking(pio0, 0, 0);) I expect to see no pulses, however as already mentioned I am seeing a short pulse which I think is 1clk cycle. Can anybody help me understand this?

Statistics: Posted by mangodan2003 — Tue Feb 25, 2025 10:37 pm — Replies 0 — Views 48



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